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copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com f eatures z 20-pin tssop package z 1.8 v to 3.3 v supply z 24-bit conversion / 96 khz sample rate z 98 db dynamic range at 3 v supply z -88 dbfs thd+n z low power consumption ?11mw at 1.8v z up to 32 db gain ? 20 db gain step ? 12 db variable input gain, 1 db steps ? changes made at zero crossings z stereo inputs z digital volume control ? 96 db attenuation, 1 db step size ?mute ? soft ramping z 2:1 input mux d escription the cs53l32a is a highly integrated, 24-bit, 96 khz au- dio adc providing stereo analog-to-digital converters using delta-sigma conversion techniques. this device in- cludes volume control and lin e level inputs in a 20-pin tssop package. the cs53l32a is based on delta-sigma modulation al- lowing infinite adjustment of the sample rate between 2 khz and 100 khz simply by changing the master clock frequency. the cs53l32a contains adjustable analog gain, a 2:1 input mux, and digital attenuation. the cs53l32a operates from a +1.8 v to +3.3 v supply. these features are ideal for portable mp3 players, md recorders/players, digital camcorders, pdas, set-top boxes, and other portable sy stems that require extreme- ly low power consumption in a minimum of space. ordering in formation CS53L32A-KZ 20-pin tssop -10 to 70 c CS53L32A-KZz 20-pin tssop -10 to 70 c lead free cs53l32a-bz 20-pin tssop -40 to 85 c cdb53l32a evaluation board i i scl/cclk/ sda/cdin/dif control port rst lrck sclk serial port mclk va gnd vq filt+ ref_gnd ain_l1 ain_l2 ain_r1 ain_r2 adc adc digital filters attenuator 0-96 db sdout ad0/cs/div attenuator 0-96 db gain gain afltl afltr chsel vl cs53l32a low voltage, stereo a/d converter oct ?04 ds513f1
cs53l32a 2 ds513f1 table of contents 1. characteristics/specifications .... ............................................................................. 4 analog characteristics ................................................................................................ 4 analog characteristics ................................................................................................ 5 power and thermal characteristics....................................................................... 8 digital characteristics ................................................................................................. 9 absolute maximum ratings ........................................................................................... 9 recommended operating conditions ....................................................................... 9 switching characteristics ........................................................................................ 10 switching characteristics - control port - two wire mode....................... 12 switching characteristics - control port - spi mode.................................... 13 2. typical connection diagram .................................................................................... 14 3. register quick reference .......................................................................................... 15 3.1 i/o and power control (address 01h) ............................................................................... 15 3.2 interface control (address 02h) ........................................................................................ 15 3.3 analog i/o control (address 03h) ..................................................................................... 16 3.4 left channel digital volume control (address 04h).......................................................... 17 3.5 right channel digital volume control (address 05h) ....................................................... 17 3.6 analog gain control (address 06h) .................................................................................. 17 3.7 clip detection status (address 07h) ................................................................................. 17 4. register description .................................................................................................... 18 4.1 gain enable ................................................................................................................ ...... 18 4.2 analog input multiplexer ................................................................................................... 18 4.3 power-down ................................................................................................................. .... 19 4.4 control port enable........................................................................................................ ... 19 4.5 master clock divide ........................................................................................................ .. 20 4.6 master clock ratio......................................................................................................... ... 20 4.7 master mode ................................................................................................................ ..... 21 4.8 digital interface format................................................................................................... .. 21 4.9 left/right channel mute ................................................................................................... 2 2 4.10 soft ramp and zero cross enable................................................................................. 22 4.11 independent volume control enable.............................................................................. 23 4.12 left channel volume = right channel volume .............................................................. 24 4.13 high-pass filter freeze .................................................................................................. 2 4 4.14 volume control ............................................................................................................ ... 25 4.15 left/right analog gain.................................................................................................... 26 4.16 clip detection............................................................................................................ ...... 26 5. pin description ........................................................................................................... ...... 27 6. pin description ........................................................................................................... ...... 28 6. pin description ........................................................................................................... ...... 28 6. applications .............................................................................................................. ........ 30 6.1 grounding and power supply decoupling ....................................................................... 30 6.2 oversampling modes ....................................................................................................... 3 0 6.3 recommended power-up sequence ............................................................................... 30 7. control port interface ............................................................................................. 30 7.1 spi mode .................................................................................................................. ....... 30 7.2 two wire mode ............................................................................................................. ... 31 7.3 memory address pointer (map) ....................................................................................... 31 8. parameter definitions .................................................................................................. 38 9. references ................................................................................................................ ........ 38 10. package dimensions .... ................................................................................................. 39 11. change history .... ....................................................................................................... ... 40
cs53l32a ds513f1 3 list of figures figure 1. sclk to lrck and sdout, slave mode ..................................................................... 11 figure 2. sclk to lrck and sdout, master mode ................................................................... 11 figure 3. relationship required between lrck and mclk in slave mode ................................ 11 figure 4. control port timing - two wire mode............................................................................ 12 figure 5. control port timing - spi mode ..................................................................................... 13 figure 6. typical connection diagram.......................................................................................... 1 4 figure 7. control port timing, spi mode ...................................................................................... 32 figure 8. control port timing, two wire mode............................................................................. 32 figure 9. base-rate stopband rejection...................................................................................... 33 figure 10. base-rate transition band.......................................................................................... 3 3 figure 11. base-rate transition band (detail) ............................................................................. 33 figure 12. base-rate passband ripple........................................................................................ 33 figure 13. high-rate stopband rejection .................................................................................... 33 figure 14. high-rate transition band........................................................................................... 33 figure 15. high-rate transition band (detail) .............................................................................. 34 figure 16. high-rate passband ripple......................................................................................... 34 figure 17. line input test circuit ............................................................................................. ..... 34 figure 18. cs53l32a control port mode - serial audio format 0 (i 2 s) ....................................... 34 figure 19. cs53l32a control port mode - serial audio format 1 ............................................... 35 figure 20. cs53l32a control port mode - serial audio format 3 ............................................... 35 figure 21. cs53l32a control port mode - serial audio format 4 ............................................... 35 figure 22. cs53l32a control port mode - serial audio format 5 ............................................... 36 figure 23. cs53l32a control port mode - serial audio format 6 ............................................... 36 figure 24. cs53l32a stand-alone mode - serial audio format 0 (i 2 s) ...................................... 36 figure 25. cs53l32a stand-alone mode - serial audio format 1............................................... 37 list of tables table 1. analog input options.................................................................................................. ..... 18 table 2. power-down enable ..................................................................................................... .. 19 table 3. control port enable................................................................................................... ...... 19 table 4. master clock divide select ............................................................................................ .20 table 5. mclk/lrck ratios ...................................................................................................... .. 20 table 6. master/slave mode selection ......................................................................................... 21 table 7. digital interface format.............................................................................................. ..... 21 table 8. left/right channel mute enable ..................................................................................... 22 table 9. analog volume control ................................................................................................. .. 23 table 10. digital volume control ............................................................................................... ... 23 table 11. independent volume control enable ............................................................................ 23 table 12. high-pass filter enable .............................................................................................. .. 24 table 13. example volume settings ............................................................................................. 2 5 table 14. example gain settings................................................................................................ .. 26 table 15. clip detection status bits........................................................................................... ... 26 table 16. common clock frequencies......................................................................................... 28 table 17. digital interface format - dif (stand-alone mode)....................................................... 28 table 18. channel select options ............................................................................................... .28 table 19. revision table ....................................................................................................... ....... 40
cs53l32a 4 ds513f1 1. characteristics/specifications analog characteristics (t a = 25 c; logic ?1? = vl = 1.8 v; logic ?0? = gnd = 0 v; mclk = 12.288 mhz; fs for base-rate mode = 48 khz, sclk = 3.072 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified. fs for high-rate mode = 96 khz, sclk = 6.144 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified. input signal is a 997 hz sine wave.) parameter symbol base-rate mode high-rate mode unit min typ max min typ max CS53L32A-KZ/kzz analog input characteristics for va = 1.8 v dynamic range a-weighted unweighted 88 85 93 90 - - 89 86 94 91 - - db db total harmonic distortion + noise (note 1) 18 to 24-bit -1 db -20 db -60 db 16-bit -1 db -20 db -60 db thd+n - - - - - - -88 -70 -30 -86 -68 -28 -83 - - - - - - - - - - - -88 -71 -31 -86 -68 -28 -83 - - - - - db db db db db db dynamic range (pga on)* 0 db gain a-weighted unweighted 12 db gain a-weighted unweighted - - - - 90 87 85 82 - - - - - - - - 89 86 86 83 - - - - db db db db total harmonic distortion + noise (pga on)* (note 1) 0 db gain 18 to 24-bit -1 db 12 db gain 18 to 24-bit -1 db thd+n - - 85 83 - - - - 84 82 - - db db CS53L32A-KZ/kzz analog input characteristics for va = 3.0 v dynamic range a-weighted unweighted 91 88 96 93 - - 93 90 98 95 - - db db total harmonic distortion + noise (note 1) 18 to 24-bit -1 db -20 db -60 db 16-bit -1 db -20 db -60 db thd+n - - - - - - -88 -73 -33 -86 -68 -28 -83 - - - - - - - - - - - -85 -75 -35 -83 -65 -28 -80 - - - - - db db db db db db dynamic range (pga on)* 0 db gain a-weighted unweighted 12 db gain a-weighted unweighted - - - - 93 90 88 85 - - - - - - - - 92 89 89 86 - - - - db db db db
cs53l32a ds513f1 5 analog characteristics (continued) parameter symbol base-rate mode high-rate mode unit min typ max min typ max total harmonic distortion + noise (pga on)* (note 1) 0 db gain 18 to 24-bit -1 db 12 db gain 18 to 24-bit -1 db thd+n - - 78 73 - - - - 77 76 - - db db CS53L32A-KZ/kzz analog input characteristics for va=1.8 v - 3.3 v interchannel isolation 1 khz - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db offset error with high pass filter - - 0 - - 0 lsb full scale input voltage -5% va/3.6 +5% -5% va/3.6 +5% vrms gain drift - 100 - - 100 - ppm/c input resistance 10 - - 10 - - k ? input capacitance - - 15 - - 15 pf cs53l32a-bz analog input characteristics for va = 1.8 v dynamic range a-weighted unweighted 86 83 93 90 - - 87 84 94 91 - - db db total harmonic distortion + noise (note 1) 18 to 24-bit -1 db -20 db -60 db 16-bit -1 db -20 db -60 db thd+n - - - - - - -88 -70 -30 -86 -68 -28 -81 - - - - - - - - - - - -88 -71 -31 -86 -68 -28 -81 - - - - - db db db db db db dynamic range (pga on)* 0 db gain a-weighted unweighted 12 db gain a-weighted unweighted - - - - 90 87 85 82 - - - - - - - - 89 86 86 83 - - - - db db db db total harmonic distortion + noise (pga on)* (note 1) 0 db gain 18 to 24-bit -1 db 12 db gain 18 to 24-bit -1 db thd+n - - 85 83 - - - - 84 82 - - db db cs53l32a-bz analog input characteristics for va = 3.0 v dynamic range a-weighted unweighted 89 86 96 93 - - 91 88 98 95 - - db db
cs53l32a 6 ds513f1 total harmonic distortion + noise (note 1) 18 to 24-bit -1 db -20 db -60 db 16-bit -1 db -20 db -60 db thd+n - - - - - - -88 -73 -33 -86 -68 -28 -81 - - - - - - - - - - - -85 -75 -35 -83 -65 -28 -78 - - - - - db db db db db db dynamic range (pga on)* 0 db gain a-weighted unweighted 12 db gain a-weighted unweighted - - - - 93 90 88 85 - - - - - - - - 92 89 89 86 - - - - db db db db total harmonic distortion + noise (pga on)* (note 1) 0 db gain 18 to 24-bit -1 db 12 db gain 18 to 24-bit -1 db thd+n - - 78 73 - - - - 77 76 - - db db * pga = programmable gain amplifier cs53l32a-bz analog input characteristics for va=1.8 - 3.3v interchannel isolation 1 khz - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db offset error with high pass filter - - 0 - - 0 lsb full scale input voltage -7% va/3.6 +7% -7% va/3.6 +7% vrms gain drift - 100 - - 100 - ppm/c input resistance 10 - - 10 - - k ? input capacitance - - 15 - - 15 pf programmable gain characteristics gain step size - 1.0 - - 1.0 - db absolute gain step error - - 0.3 - - 0.3 db a/d decimation filter characteristics (note 2) passband (note 3) 0 - 23.5 0 - 47.5 khz passband ripple -0.08 - +0.17 -0.09 - 0 db stopband (note 3) 27.5 - - 64.1 - - khz stopband attenuation (note 4) -60.3 - - -48.4 - - db group delay (fs = output sample rate) (note 5) t gd - 10/fs - - 2.7/fs - s group delay variation vs. frequency ? t gd - - 0.03 - - 0.007 s parameter symbol base-rate mode high-rate mode unit min typ max min typ max
cs53l32a ds513f1 7 notes: 1. referenced to typical full-scale input voltage (0.5 vrms). 2. filter response is not tested but is guaranteed by design. 3. filter characteristics scale with output sample rate. for output sample rates, fs, other than 48 khz, the 0.01 db passband edge is 0.4535x fs and the stopband edge is 0.625x fs. 4. the analog modulator samples the input at 6.144 mhz for an fs equal to 48 khz. there is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 mhz 21.8 khz where n = 0,1,2,3...). 5. group delay for fs = 48 khz, t gd = 10/48 khz = 208 s. high pass filter characteristics frequency response -3 db (note 2) -0.1 db - - 3.7 24.2 - - - - 3.7 24.2 - - hz hz phase deviation @ 20 hz (note 2) - 10 - - 10 - degree passband ripple (note 2) - - 0.17 - - 0.09 db parameter symbol base-rate mode high-rate mode unit min typ max min typ max
cs53l32a 8 ds513f1 power and thermal characteristics notes: 6. power down mode is defined as the chip being held in reset with mclk running. to lower power consumption further, remove mclk. 7. valid with the recommended capacitor values on filt+ and vq as shown in figure 6. base-rate mode high-rate mode parameters symbol min typ max min typ max units power supplies power supply current- va=1.8 v normal operation vl=1.8 v i a i d_io - - 6.0 150 - - - - 7.6 300 - - ma a power supply current- va=1.8 v power down mode (note 6) vl=1.8 v i a i d_io - - 100 0 - - - - 250 0 - - a a power supply current- va=3.0 v normal operation vl=3.0 v i a i d_io - - 9 260 - - - - 11.5 520 - - ma a power supply current- va=3.0 v power down mode vl=3.0 v i a i d_io - - 250 0 - - - - 500 0 - - a a total power dissipation- all supplies=1.8 v normal operation all supplies=3.0 v - - 11 28 12 31 - - 14.5 36 16 40 mw mw package thermal resistance ja -75- -75-c/watt power supply rejection ratio (1 khz) (note 7) (60 hz) psrr - - 60 40 - - - - 60 40 - - db db
cs53l32a ds513f1 9 digital characteristics (t a = 25 c; vl = 1.7 v - 3.6 v; gnd = 0 v) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0v; all voltages with respect to ground.) parameters symbol min typ max units high-level input voltage v ih 0.7vl - - v low-level input voltage v il - - 0.3vl v high-level output voltage v oh 0.7vl - - v low-level output voltage v ol - - 0.3vl v leakage current i in --10 a input capacitance - 8 - pf parameters symbol min max units dc power supplies: positive analog digital i/o va vl -0.3 -0.3 4.0 4.0 v v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 vl+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units ambient temperature t a -10 - 70 c dc power supplies: positive analog digital i/o va vl 1.7 1.7 - - 3.6 3.6 v v
cs53l32a 10 ds513f1 switching characteristics (t a = -10 to 70 c; va = 1.7 v - 3.6 v; inputs: logic 0 = gnd, logic 1 = vl, c l = 20 pf) 8. there must be exactly 32, 48, 64, or 128 sclk periods per lrck transition. 9. slave mode operation requires an exact 50% duty cycle. otherwise the cs53l32a will produce erroneous data. parameters symbol min typ max units input sample rate base rate mode high rate mode fs fs 2 50 - - 50 100 khz khz mclk pulse width high mclk/lrck = 1024 8 - - ns mclk pulse width low mclk/lrck = 1024 8 - - ns mclk pulse width high mclk/lrck = 768 10 - - ns mclk pulse width low mclk/lrck = 768 10 - - ns mclk pulse width high mclk/lrck = 512 15 - - ns mclk pulse width low mclk/lrck = 512 15 - - ns mclk pulse width high mclk / lrck = 384 or 192 21 - - ns mclk pulse width low mclk / lrck = 384 or 192 21 - - ns mclk pulse width high mclk / lrck = 256 or 128 31 - - ns mclk pulse width low mclk / lrck = 256 or 128 31 - - ns master mode sclk falling to lrck edge t slrd -20 - 20 ns sclk falling to sdout valid t sdo 0 - 20 ns sclk duty cycle 40 50 60 % slave mode lrck duty cycle notes 8, 9 - 50 - % rise time of both lrck and sclk t r - - 10 ns fall time of both lrck and sclk t f - - 10 ns sclk period base rate mode high rate mode t sclkw t sclkw - - - - ns ns sclk falling to lrck edge t slrd -20 - 20 ns sclk falling to sdout valid base rate mode high rate mode t dss t dss - - - - ns ns note: when operating the cs53l32a revision c in slave mode, base rate mode, certain timing requirements must be met in addition to those specified above. the required timing relationship between the mclk and lrck is shown in figures 3. an mclk rising edge cannot lead an lrck transition by 6ns to 10ns. 1 128 () fs --------------------- - 1 64 () fs ------------------ 1 (512)fs 1 (256)fs
cs53l32a ds513f1 11 sclk lrck sdout t sclkl t slrd t dss msb t sclkh t sclkw figure 1. sclk to lrck and sdout, slave mode sclk lrck sdout t slrd t sdo msb msb-1 figure 2. sclk to lrck and sdout, master mode lrck input 6 ns 10 ns no rising edge of mclk allowed within this timing window. mclk input figure 3. relationship required between lrck and mclk in slave mode
cs53l32a 12 ds513f1 switching characteristics - cont rol port - two wire mode (t a = 25 c; vl = 1.7 v - 3.6 v; inputs: logic 0 = gnd, logic 1 = vl, c l = 30 pf) note: 10. data must be held for sufficient time to bridge the transition time, t f , of scl . parameter symbol min max unit two wire mode scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 10) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl t rc -25ns fall time of scl t fc -25ns rise time of sda t rd -1us fall time of sda t fd - 300 ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 4. control port timing - two wire mode t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst
cs53l32a ds513f1 13 switching characteristics - co ntrol port - spi mode (t a = 25 c; vl = 1.7v - 3.6v; inputs: logic 0 = gnd, logic 1 = vl, c l = 30 pf) notes: 11. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 12. data must be held for sufficient time to bridge the transition time of cclk. 13. for f sclk < 1 mhz. parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 11) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 12) t dh 15 - ns rise time of cclk and cdin (note 13) t r2 - 100 ns fall time of cclk and cdin (note 13) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 5. control port timing - spi mode
cs53l32a 14 ds513f1 2. typical connection diagram mclk lrck sclk rst sda/cdin/dif scl/cclk/chsel ad0/cs/div gnd c/ digital audio source va filt+ ref_gnd cs53l32a 1.8 to 3.3 v supply *ferrite bead 1.0 f 0.1 f + 1.0 f 1.8 to 3.3 v supply 1.0 f + vl *ferrite bead + 5 1 13 16 6 mode configuration 0.47 f 150 ? 0.47 f 150 ? 0.47 f 150 ? 0.01 f 0.47 f 150 ? ain_l1 ain_r1 ain_l2 ain_r2 ** ** ** ** sdout **optional if analog input circuit is biased within 5% of cs53l32a nominal bias voltage * optional vq 1.0 f 19 18 17 15 14 afltl 2 7 3 4 20 9 10 8 12 afltr 11 0.01 f 0.01 f 0.01 f 0.1 f 1 nf 1 nf + 0.1 f 0.1 f figure 6. typical connection diagram
cs53l32a ds513f1 15 3. register quick reference ** ?default? ==> bit status after power-up-sequence or reset. 3.1 i/o and power control (address 01h) boost 20 db digital gain default = ?0? 0 - disabled 1 - enabled ainmux analog input multiplexer default =?0?. 0 - ain_l1/ain_r1 direct to a/d (default) 1 - ain_l2/ain_r2 direct to a/d 2 - ain_l2/ain_r2 through pga to a/d 3 - reserved pdn power-down default =?1?. 0 - disabled 1 - enabled cp_en control port enable default =?0?. 0 - disabled 1 - enabled 3.2 interface control (address 02h) mclkdiv master clock divider default =?0?. 0 - disabled 1 - enabled ratio1-0 master clock ratio default =?0?. 0 - 128x (default) 1 - 192x 2 - 256x 3 - 384x master master mode default =?0?. 0 - slave mode 1 - master mode 76543210 reserved boost ainmux1 ainmux0 reserved reserved pdn cp_en 00000010 76543210 reserved mclkdiv ratio1 ratio0 master dif2 dif1 dif0 00000000
cs53l32a 16 ds513f1 dif2-0 digital interface format default = ?0?. 0 - i 2 s, up to 24-bit data, data valid on positive edge of slck (default) 1 - left justified, up to 24-bit data, data valid on positive edge of slck 2 - reserved 3 - right justified, 16-bit data, data valid on positive edge of slck 4 - right justified, 24-bit data, data valid on positive edge of slck 5 - right justified, 18-bit data, data valid on positive edge of slck 6 - right justified, 20-bit data, data valid on positive edge of slck 7 - reserved 3.3 analog i/o control (address 03h) mutel left channel mute default = ?0?. 0 - disabled 1 - enabled muter right channel mute default = ?0?. 0 - disabled 1 - enabled soft soft digital/analog volume control default = ?1?. 0 - disabled 1 - enabled zc analog zero cross detection control default = ?1?. 0 - disabled 1 - enabled indvc independent volume control enable default = ?0?. 0 - disabled 1 - enabled l=r left channel volume = right channel volume default = ?0?. 0 - left channel volume is determined by the left channel volume control registers and right channel volume is determined by the right channel volume control registers. 1 - left and right channel volumes are determined by the left channel volume control registers and the right channel volume control registers are ignored. hpfreeze high-pass filter freeze default = ?0?. 0 - disabled 1 - enabled 76543210 mutel muter soft zc reserved indvc l=r hpfreeze 00110000
cs53l32a ds513f1 17 3.4 left channel digital volume control (address 04h) 3.5 right channel digital volume control (address 05h) vol7-0 volume default = ?0?. (refer to table 13) 3.6 analog gain control (address 06h) lvol3-0 left analog gain default = ?0?. (refer to table 14) rvol3-0 right analog gain default = ?0?. (refer to table 14) 3.7 clip detection status (address 07h) clip_l_flag left channel clip detection clip_r_flag right channel clip detection default = ?0?. 0 - no clipping detected 1 - clipping detected 76543210 vol7 vol6 vol5 vol4 vol3 vo l2 vol1 vol0 00000000 76543210 lvol3 lvol2 lvol1 lvol0 rvol3 rvol2 rvol1 rvol0 00000000 76543210 reserved reserved reserved reserved reserved reserved clip_l_flag clip_r_flag 00000000
cs53l32a 18 ds513f1 4. register description 4.1 gain enable i/o and power control register (address 01h) access: r/w in two wire mode and write only in spi. default: 0 - disabled function: applies a 20 db digital gain to the input signal, regardless of the input path. 4.2 analog input multiplexer i/o and power control register (address 01h) access: r/w in two wire mode and write only in spi. default: 0 - ain_l1/ain_r1 direct to a/d function: the analog input multiplexer selects the input channel as well as the input path associated with vari- ous gain stages. 76543210 reserved boost ainmux1 ainmux0 reserved reserved pdn cp_en 76543210 reserved boost ainmux1 ainmux0 reserved reserved pdn cp_en ainmux mode 0 ain_l1/ain_r1 direct to a/d 1 ain_l2/ain_r2 direct to a/d 2 ain_l2/ain_r2 through pga to a/d 3 reserved table 1. analog input options
cs53l32a ds513f1 19 4.3 power-down i/o and power control register (address 01h) access: r/w in two wire mode and write only in spi. default: 1 - enabled function: the entire device will enter a low-power state whenever this function is activated. the power-down bit defaults to ?enabled? on power-up and must be dis abled before normal operation will begin. the contents of the control registers are retained when this mode is enabled. 4.4 control port enable i/o and power control register (address 01h) access: r/w in two wire mode and write only in spi. default: 0 - disabled function: the cs53l32a will enter control port mode when this bit is enabled. stand-alone is the default power up mode. see section 6.3, recommended power-up sequence, for more details. 76543210 reserved boost ainmux1 ainmux0 reserved reserved pdn cp_en pdn mode 0 disabled 1 enabled table 2. power-down enable 76543210 reserved boost ainmux1 ainmux0 reserved reserved pdn cp_en cp_en mode 0disabled 1 enabled table 3. control port enable
cs53l32a 20 ds513f1 4.5 master clock divide interface control register (address 02h) access: r/w in two wire mode and write only in spi. default: 0 - disabled function: divides mclk by two prior to all other chip circuitry. 4.6 master clock ratio interface control register (address 02h) access: r/w in two wire mode and write only in spi. default: 0 - 128x function: sets the ratio of mclk to lrck. 76543210 reserved mclkdiv ratio1 ratio0 master dif2 dif1 dif0 mclkdiv mode 0 disabled 1 enabled table 4. master clock divide select 76543210 reserved mclkdiv ratio1 ratio0 master dif2 dif1 dif0 ratio1,0 mclk/lrck ratio (mclkdiv=0) mclk/lrck ratio (mclkdiv=1) 0 128x 256x 1 192x 384x 2 256x 512x 3 384x 768x table 5. mclk/lrck ratios
cs53l32a ds513f1 21 4.7 master mode interface control register (address 02h) access: r/w in two wire mode and write only in spi. default: 0 - slave mode function: configures the device for master or slave operation when in control port mode. 4.8 digital interface format interface control register (address 02h) access: r/w in two wire mode and write only in spi. default: 0 - format 0 (i 2 s, up to 24-bit data, data valid on positive edge of sclk) function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 18 through 21. 76543210 reserved mclkdiv ratio1 ratio0 master dif2 dif1 dif0 master mode 0 slave mode 1 master mode table 6. master/slave mode selection 76543210 reserved mclkdiv ratio1 ratio0 master dif2 dif1 dif0 dif2 dif1 dif0 description format figure 000 i 2 s, up to 24-bit data, data valid on positive edge of sclk 018 0 0 1 left justified, up to 24-bit data, data valid on positive edge of sclk 1 19 0 1 0 reserved 2 - 0 1 1 right justified, 16-bit data, data valid on positive edge of sclk 3 18 1 0 0 right justified, 24-bit data, data valid on positive edge of sclk 4 19 1 0 1 right justified, 18-bit data, data valid on positive edge of sclk 5 20 1 1 0 right justified, 20-bit data, data valid on positive edge of sclk 6 21 1 1 1 reserved 7 - table 7. digital interface format
cs53l32a 22 ds513f1 4.9 left/right channel mute analog i/o control (address 03h) access: r/w in two wire mode and write only in spi. default: 0 - disabled function: digital mute of the left and right channels. 4.10 soft ramp and zero cross enable analog i/o control register (address 03h) access: r/w in two wire mode and write only in spi. default: 11 - soft ramp and zero cross enabled function: soft ramp enable soft ramp allows level changes, both muting and attenuation, to be implemented via an incremental ramp. digital volume control is ramped from the current level to the new level at a rate of 1/8 db per left/right clock period. analog volume control is ramped in 1 db steps every 8 left/right clock periods in base rate mode, and 1 db every 16 left/right clock periods in high rate mode. zero cross enable zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period of 512 sample periods in brm or 1024 sample periods in hrm (approximately 10.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross func- tion is independently monitored and implemented for each channel. 76543210 mutel muter soft zc reserved indvc l=r hpfreeze mutel/ muter mode 0 disabled 1 enabled table 8. left/right channel mute enable 76543210 mutel muter soft zc reserved indvc l=r hpfreeze
cs53l32a ds513f1 23 soft ramp and zero cross enable soft ramp and zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1 db steps and be implemented on a signal zero crossing. the level change will occur after a timeout period of 512 sample periods in brm or 1024 sample periods in hrm (ap- proximately 10.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. . 4.11 independent volume control enable analog i/o control register (address 03h) access: r/w in two wire mode and write only in spi. default: 0 - enabled function: when this function is disabled, the ain_l and ain_r volume levels are controlled by the left and right volume control registers and the independent analog gain control registers are ignored. when this function is enabled, the volume levels are determined by both the volume control registers and the independent analog gain control registers. soft/zc analog volume control modes 00 change volume immediately 01 change volume at next zero cross time 10 change volume in 1 db steps 11 change volume in 1 db steps at every zero cross time table 9. analog volume control soft digital volume control modes 0 change volume immediately 1 change volume in1/8 db steps table 10. digital volume control 76543210 mutel muter soft zc reserved indvc l=r hpfreeze indvc mode 0 enabled 1frozen table 11. independent volume control enable
cs53l32a 24 ds513f1 4.12 left channel volume = right channel volume analog i/o control (address 03h) access: r/w in two wire mode and write only in spi. default: 0 - disabled function: when this function is disabled, the left channel volume is determined by the left channel volume con- trol register and right channel volume is determined by the right channel volume control register. when enabled, the left and right channel volumes are determined by the left channel volume control register and the right channel volume control register is ignored. 4.13 high-pass filter freeze analog i/o control register (address 03h) access: r/w in two wire mode and write only in spi. default: 0 - enabled function: the high-pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. if the hpfreeze bit is taken low during normal operation, the current value of the dc offset is frozen and this dc offset will continue to be subtracted from the conversion result. this feature makes it possible to perform a system calibration by: 1) removing the signal source at the input to the subsystem containing the cs53l32a, 2) running the cs53l32a with the hpfreeze bit high until the filter settles, approximately one second, 3) taking the hpfreeze bit low, thus disabling the high-pass filter and freezing the stored dc offset. a system calibration performed in this way will elim inate offsets anywhere in the signal path between the calibration point and the cs53l32a. 76543210 mutel muter soft zc reserved indvc l=r hpfreeze 76543210 mutel muter soft zc reserved indvc l=r hpfreeze hpfreeze mode 0 enabled 1frozen table 12. high-pass filter enable
cs53l32a ds513f1 25 4.14 volume control left channel volume control register (address 04h) right channel volume control register (address 05h) access: r/w in two wire mode and write only in spi. default: 0 - 0 db (no attenuation) function: the volume control allows the user to alter the signal level in 1 db increments from +12 to -96 db, when the indvc bit is disabled. when indvc is enabled, the volume control can be altered in 1 db increments from 0 to -96 db. volume settings are decoded as shown in table 13, using a 2?s complement code. the volume changes are implemented as dictated by the soft and zero cross bits in the analog i/o control register. all volume settings less than -96 db are equivalent to muting the channel. 76543210 vol7 vol6 vol5 vol4 vol3 vo l2 vol1 vol0 binary code decimal value volume setting 00001010 12 +12 db 00000111 7 +7 db 00000000 0 0 db 11000100 -60 -60 db 10100110 -90 -90 db table 13. example volume settings
cs53l32a 26 ds513f1 4.15 left/right analog gain adc independent analog gain control register (address 06h) access: r/w in two wire mode and write only in spi. default: 0 - 0 db (no gain) function: the level of the left and right analog channels can be adjusted in 1 db increments as dictated by the soft ramp and zero cross bits from 0 to +12 db when routed through the pga via the ainmux bits in control port mode or the ch_sel pins in stand-alone mode. levels are decoded as shown in table 14. levels above +12 db are interpreted as +12 db. 4.16 clip detection clip detection status register (address 07h) access: read only in two wire mode and unavailable in spi. default: 0 - no clipping detected function: the clip flags indicate when there is an over-range condition anywhere in the cs53l32a internal signal path. these bits are ?sticky?. they constantly monitor the adc signal path and are set to 1 when an over- range condition occurs. they are reset to 0 when read. 76543210 lvol3 lvol2 lvol1 lvol0 rvol3 rvol2 rvol1 rvol0 binary code decimal value volume setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db table 14. example gain settings 76543210 reserved reserved reserved reserved reserved reserved clip_l_flag clip_r_flag clip_l_flag clip_r_flag condition 0 signal within normal range 1 signal is over-range table 15. clip detection status bits
cs53l32a ds513f1 27 5. pin description interface power vl rst reset master clock mclk vq quiescent voltage serial clock sclk ain_l1 analog input 1 left serial audio data out sdout ain_r1 analog input 1 right analog power va ref_gnd reference ground ground gnd ain_l2 analog input 2 left left/right clock lrck ain_r2 analog input 2 right ad0/cs /div ad0/cs /div filt+ positive voltage reference sda/cdin/dif sda/cdin/dif afltl anti-aliasing capacitor scl/cclk/chsel scl/cclk/chsel afltr anti-aliasing capacitor 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 20 19 18 17 16 15 14 13 interface power 1 vl ( input ) - digital interface power supply. typically 1.8 to 3.3 vdc. master clock 2 mclk ( input ) - the master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in base rate mode (brm) and 128x, 192x, 256x, 384x the input sample rate in high rate mode (hrm). table 16 illustrates several standard audio sample rates and the required master clock frequencies. serial clock 3 sclk ( input / output ) - clocks the individual bits of the serial data out of the sdout pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dif2-0 bytes when in control port mode or by the dif1-0 pins when in stand-alone mode. serial audio data out 4 sdout ( output ) - this pin serves two functions. first: two's complement msb-first serial data is output on this pin. the data is clocked out of sdout via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the dif2-0 bytes when in control port mode or by the dif pin when in stand-alone mode. second: in stand-alone mode, master/slave mode selection is determined, at start-up, by a 47 kohm pull-up/pull-down on this line. a pull-up to vl selects master mode and a pull-down to gnd selects slave mode. analog power 5 va ( input ) - analog power supply. typically 1.8 to 3.3 vdc. ground 6 gnd ( input ) - ground reference. left/right clock 7 lrck ( input / output ) - the left/right clock determines which channel is cur- rently being output on the serial audio data line sdout. the frequency of the left/right clock must be at the input sample rate. the required relation- ship between the left/right clock, serial clock and serial data is defined by the dif2-0 bytes when in control port mode or by the dif pin when in stand-alone mode.
cs53l32a 28 ds513f1 address bit 8 ad0/cs (control port mode) ( input ) - in two wire mode, ad0 is a chip address bit. cs is used to enable the control port interface in spi mode. mclk divide enable 8 div (stand-alone mode) ( input ) - when high, the chip will enter high rate mode. when this pin is low, the chip will enter base rate mode. serial control data i/o 9 sda/cdin (control port mode) ( input / output ) - in two wire mode, sda is a data i/o line. cdin is the input data line for the control port interface in spi mode. digital interface format 9 dif (stand-alone mode) ( input ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format. serial control interface clock 10 scl/cclk (control port mode) ( input ) - clocks the serial control data into or from sda/cdin/dif. channel select 10 chsel (stand-alone mode) ( input) - the analog data path is determined by the channel select bit. these options are detailed in table 18. anti-aliasing capacitors 11, 12 afltr, afltl ( output ) - anti-aliasing capacitors for the left and right chan- nels. an external capacitor is required from afltr and afltl to ground, as shown in figure 5. afltr and afltl are not intended to supply external current, and any current drawn from these pins will alter device perfor- mance. positive voltage reference 13 filt+ ( output) - positive reference for internal sampling circuits. an external capacitor is required from filt+ to ground, as shown in figure 6. the rec- ommended value will typically provide 60 db of psrr at 1 khz and 40 db of psrr at 60 hz. filt+ is not intended to supply external current. filt+ has a typical source impedance of 250 k ? and any current drawn from this pin will alter device performance. analog inputs 14, 15, 17, and 18 ain_r1, ain_l1, ain_r2, ain_l2 ( input ) - channel 1/channel 2 analog inputs. sample rate (khz) mclk (mhz) hrm brm 128x 192x 256x* 384x* 256x 384x 512x 768x* 1024x* 32 4.0960 6.1440 8.1920 12.2880 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 5.6448 8.4672 11.2896 16.9344 11.2896 16.9344 22.5792 32.7680 45.1584 48 6.1440 9.2160 12.2880 18.4320 12.2880 18.4320 24.5760 36.8640 49.1520 64 8.1920 12.2880 16.3840 24.5760 - - - - - 88.2 11.2896 16.9344 22.5792 33.8688 - - - - - 96 12.2880 18.4320 24.5760 36.8640 - - - - - * mclkdiv = 1 in control port mode or div= hi when in stand-alone mode table 16. common clock frequencies dif description 0 i 2 s, up to 24-bit data 1 left justified, up to 24-bit data table 17. digital interface format - dif (stand-alone mode) chsel description 0 channel 1 directly to a/d 1 channel 2 with 32db of gain table 18. channel select options
cs53l32a ds513f1 29 reference ground 16 ref_gnd ( input ) - ground reference for the internal sampling circuits. must be connected to ground. quiescent voltage 19 vq ( output ) - filter connection for internal a/d converter quiescent refer- ence voltage. a capacitor must be connected from vq to ground. vq is not intended to supply external current. vq has a typical source impedance of 250 k ? and any current drawn from this pin will alter device performance. reset 20 rst ( input ) - the device enters a low power mode and all internal registers are reset to their default settings, including the control port, when low. when high, the control port becomes operational and the pdn bit must be cleared before normal operation will occur. the control port cannot be accessed when reset is low.
cs53l32a 30 ds513f1 6. applications 6.1 grounding and power supply decoupling as with any high resolution converter, the cs53l32a requires careful attention to power supply and grounding arrangements to optimize performance. figure 6 shows the recommended power arrangement with va and vl connected to clean supplies. decoupling capacitors should be located as close to the de- vice package as possible. 6.2 oversampling modes the cs53l32a operates in one of two oversampling modes. base rate mode supports input sample rates up to 50 khz while high rate mode supports input sample rates up to 100 khz. see table 16 for more details. 6.3 recommended power-up sequence 1) hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and vq will remain low. 2) bring rst high. the device will remain in a low power state with vq low and will initiate the stand- alone power-up sequence. the control port will be accessible at this time. if control port operation is desired, write the cp_en bit prior to the completion of the stand-alone power-up sequence, approx- imately 1024 lrck cycles. writing this bit w ill halt the stand-alone power-up sequence and initialize the control port to its default settings. the desired register settings can be loaded while keeping the pdn bit set to 1. 3) if control port mode is selected via the cp_en bit, set the pdn bit to 0 which will initiate the power- up sequence, which requires approximately 50 s. 7. control port interface the control port is used to load all the internal settings. the operation of the control port may be complete- ly asynchronous with the audio sample rate. however, to avoid potential interference problems, the con- trol port pins should remain static if no operation is required. the control port has 2 modes: spi and two wire. if two wire operation is desired, ad0/cs should be tied to vl or gnd. if the cs53l32a ever detects a high to low transition on ad0/cs after power-up, spi mode will be selected. 7.1 spi mode in spi mode, cs is the cs53l32a chip select signal, cclk is the control port bit clock, cdin is the input data line from the microcontroller and the chip address is 0010000. all signals are inputs and data is clocked in on the rising edge of cclk. all cs53l32a registers are write-only in spi mode. figure 7 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and must be 0010000. the eighth bit is a read/write indicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits are the data which will be placed into the register designated by the map. the cs53l32a has a map auto increment capability, enabled by the incr bit in the map. if incr is a zero, then the map will stay constant for successive writes. if i ncr is set to a 1, then map will auto in- crement after each byte is written, allowing block writes of successive registers.
cs53l32a ds513f1 31 7.2 two wire mode in two wire mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 8. there is no cs pin. pin ad0 forms the partial chip address and should be tied to vl or gnd as required. the upper 6 bits of the 7 bit address field must be 001000. to communicate with the cs53l32a the lsb of the chip address field, which is the first byte sent to the cs53l32a, should match the setting of the ad0 pin. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer which selects the register to be read or written. see section 7.3, memory address pointer (map) . if the operation is a read, the contents of the register pointed to by the memory address pointer will be output. setting the auto increment bit in map, allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. note: the two-wire control port mode is compatible with the i 2 c protocol. 7.3 memory address pointer (map) incr (auto map increment enable) default = ?0?. 0 - disabled 1 - enabled map0-2 (memory address pointer) default = ?000?. 76543210 incr reserved reserved reserved reserved map2 map1 map0 00000000
cs53l32a 32 ds513f1 map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 7. control port timing, spi mode sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 8. control port timing, two wire mode
cs53l32a ds513f1 33 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.42 0.44 0. 46 0.48 0.5 0.52 0. 54 0.56 0.58 0.6 frequency (normalized to fs) amplitude db figure 9. base-rate stopband rejection figure 10. base-rate transition band -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normali zed to fs) amplitude db figure 11. base-rate transition band (detail) figure 12. base-rate passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0. 5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 frequency (normalized to fs) amplitude db figure 13. high-rate stopband rejection figure 14. high-rate transition band
cs53l32a 34 ds513f1 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0. 47 0. 48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normal ized to fs) amplitude db -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude db figure 15. high-rate transition band (detail) figure 16. high-rate passband ripple gnd ain_xx 150 ? 0.47 f 0.01 f figure 17. line input test circuit lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 i 2 s, up to 24-bit data. data valid on rising edge of sclk. figure 18. cs53l32a control port mode - serial audio format 0 (i 2 s)
cs53l32a ds513f1 35 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 left justified, up to 24-bit data. data valid on rising edge of sclk. figure 19. cs53l32a control port mode - serial audio format 1 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks right justified, 16-bit data. data valid on rising edge of sclk. sclk must have at least 32 cycles per lrck period. figure 20. cs53l32a control port mode - serial audio format 3 figure 21. cs53l32a control port mode - serial audio format 4 lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel right justified, 24-bit data. data valid on rising edge of sclk. sclk must have at least 48 cycles per lrck period.
cs53l32a 36 ds513f1 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 22. cs53l32a control port mode - serial audio format 5 right justified, 18-bit data. data valid on rising edge of sclk. sclk must have at least 36 cycles per lrck period. lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 right justified, 20-bit data. data valid on rising edge of sclk. sclk must have at least 40 cycles per lrck period. figure 23. cs53l32a control port mode - serial audio format 6 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 i 2 s, up to 24-bit data. data valid on rising edge of sclk figure 24. cs53l32a stand-alone mode - serial audio format 0 (i 2 s)
cs53l32a ds513f1 37 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 left justified, up to 24-bit data. data valid on rising edge of sclk. figure 25. cs53l32a stand-alone mode - serial audio format 1
cs53l32a 38 ds513f1 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 9. references 1. ?how to achieve optimum performance from delta-sigma a/d & d/a converters? by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2. cdb53l32 evaluation board datasheet.
cs53l32a ds513f1 39 10.package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs53l32a 40 ds513f1 11.change history table 19. revision table revision date change pp1 july 2000 initial release pp2 september 2004 added part number CS53L32A-KZz, lead free package option. f1 october 2004 updated min/max specifications integrated errata er513b1 integrated errata er513b2 integrated errata er513c1 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/ cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of li ability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, life support products or other critical applications (including medical devices, aircraft systems or components and personal or automotive safety or se- curity devices). inclusion of cirrus products in such applications is understood to be fully at the customer?s risk and cir- rus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, includ- ing attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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